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Wafer acceptance testing or process parametrics are used to validate semiconductor electrical/process parameters. Wafer sort testing is done as required and includes HP8200 / EG2001 functional tests of application circuits. Wafer maps are generated based on probing. The evaluation of the emulated device is done using the same test processes used to measure the original sample part. All characterized Sarnoff parts are verified to conform to spec requirements and receive ESD evaluation. Full 5004, 5005 to MIL-STD-883
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