About GEM  |  About AME  |  
Emulation Process
  |  Wafer Foundry

Emulation Process

Fig. 1

The Emulation technology is based on families of 1.5µm and 3.5µm BiCMOS gate arrays, which are personalized by a double-level metal process. The BiCMOS gate array approach allows ICs that were originally manufactured in RTL, DTL, TTL, Schottky, CMOS and NMOS technologies to be produced from an inventory of BiCMOS base wafers. The Sarnoff Production System for emulating microcircuits is illustrated in Figure 1.

When a request for an IC part type is received, the Sarnoff designers review the part specification using available documentation and data obtained from measurement and other reverse engineering processes performed on existing parts. The data obtained from paper documentation are converted to a computer readable format and augmented by data obtained through electrical measurement of existing sample parts.

The result of the analysis is an Emulation Design Specification that satisfies the original specification, and corrects any errors or ambiguities in the original documentation. In Sarnoff’s experience, the part documentation obtained from data books, slash sheets, and OEM data are not always complete and must be verified. Sarnoff designers complete the design, including simulation at the logic and device level, as required to verify that the part specification has been satisfied. One of the bi-products of the emulation design is a VHDL (VHSIC Hardware Description Language) description of the component.

After the circuit design is completed the physical interconnection is laid out and verified using CAD software. "Personalization" interconnections are defined during the completion of the wafer fabrication. Additional metalization is added as required to satisfy current density, bussing, and other requirements to provide the complete layout data in computer-readable form for the mask set. The personalization masks are used to pattern the metal on the inventoried base wafers. Personalized wafers are probed at Sarnoff to identify electrically good die and then sent to an external assembly vendor for packaging and screening for compliance with QML requirements.

All parts are fully traceable and delivered with a certificate of conformance in compliance with customer procurement requirements. Emulation technology can be applied to replace a single IC, to replace multiple ICs, with a single device, to redefine the function and capabilities of an existing board or to combine the function of multiple boards into a single IC.