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Design

The design of the emulation circuit utilizes modern CAD tools. An electronic schematic and/or VHDL model is created and validated based on the functional verification developed during reverse engineering. In addition to logic simulation, transistor level circuits are simulated using H-SPICE to check timing centering and current/voltage matching to ensure conformance with the required electrical and delay parameters of the original device. After the circuit design is completed the physical interconnection is laid out and verified.

CIRCUIT / LOGIC

  • Mentor schematic capture
  • VHDL Logic simulation (implementing VITAL compliant simulator for accurate timing)
  • H-SPICE transistor level simulation (timing centering and current/voltage matching)

LAYOUT

  • Mentor cell layout (new cells)
  • Automated place and route cell
  • Mentor design rule layout verification

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