Arrays
Typical GEM parts are implemented using several families of 1.5 micron and 3.5 micron BiCMOS standardized base gate arrays. A typical array includes BiCMOS Input/Output Cells and a CMOS interior array. Each array incorporates special circuit elements to enable matching both propagation delay timing and interface electrical characteristics of the original device. Each emulation defines double-metal custom interconnections ("personalization") to connect the necessary logic elements for accurate emulation on the base array.
Fig. 2
GEM Gate Array showing CMOS base gate array structure and BiCMOS Input/Output interface.
1.5µm BiCMOS (5 volt)
- Small gate – 18 pins, die size 85.3 x 109
- Medium gate – 28 pins, die size 109 x 176.5
- Large gates – 48 pins, die size 219.5 x 226.4
- 1K RAM/ROM – 28 pins, die size 109.1 x 176.5
- 4K RAM/ROM – 36 pins, die size 152.1 x 209
- 11K Sea of Gates – 64 pins, die size 112.2 x 132.6
- 24K Sea of Gates – 90 pins, die size 185.2 x 191.9
1.5µm BiCMOS (Hi Power Driver)
- Small gate – 16 pins, die size 121.1 x 148.3
- 5V Input/Logic
- 100V Output
3.5µm CMOS (18 volt)
- Small gate – 18 pins, die size 85.3 x 109
- Medium gate – 28 pins, die size 109 x 176.5
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