Department of Defense requirements for microcircuits, particularly custom Application Specific Integrated Circuits (ASICs), are inhibited by unavailable or incomplete Technical Data Packages (TDPs). Even where documentation exists, it seldom contains the detailed information necessary to ensure a first-pass design success. In many cases, the only existing “data” is the packaged integrated circuit (IC). The Emulation process begins with "reverse engineering" the original device. This includes reviewing any existing documentation, electrical probing of the original circuit (Electrical RE), and physically inspecting the original part through careful delayering and high-resolution imaging (Physical RE).
Document reviews includes a thorough review of the detailed Government documents (Standard Military Drawing or slash sheet) or customer's component specification (Source Controlled Drawing) in addition to the original manufacturer's published data. The greater the information available will reduce time and increase the chance of first chance success.
Electrical Reverse Engineering
A known good, working, original part is electrically tested both functionally and every specified electrical parameter using sophisticated ATE (Automatic Test Equipment) and, when required, traditional instrumentation. Any ambiguities may require additional tests as specified by design engineer.
The resulting measurements of this original device are reviewed relative to the specification requirements and used as a baseline for the detailed design of the emulation circuit. Our electrical testing capabilities are listed below:
- Up to 512 pins
- Up to 800 MHz test cycle
- Timing accuracy +/- 200ps
MANUAL BENCH TESTING
- Drift measurements (PPM Specs)
- "Non-digital" measurements (rise times, max frequency, etc.)
- Validate any questionable ATE measurements
- Power-up modes
FULL MIL SPEC TEMPERATURE CAPABILITY
- -55 to +125 temperature conditioning and control at DUT
- Used on both ATE and bench tests
- All specified parameters measured over full temperature range
Physical Reverse Engineering
SRI has developed and demonstrated a physical reverse engineering capability for complex ICs. This reverse engineering process involves removing the silicon die from the package and carefully “deprocessing” the IC layer-by-layer and capturing each circuit layer with optical and electron-beam microscopy. Pattern recognition algorithms and image analysis techniques are then used to regenerate the original mask information used to manufacture the IC. CAD design rule and schematic verification software are then utilized to extract a component level netlist from the mask data. This is used to recreate the design specification necessary to emulate the IC using GEM/AME technology and design libraries. SRI has the capability to derive netlists, schematics and higher order design information directly from silicon die without additional technical data. This reverse engineering technique was utilized to extract the net list of a MIL-STD-1750 microprocessor chip set.